Image sensor arrays typically comprise a linear array of photosensors which raster scan an image-bearing document and convert the microscopic image areas viewed by each photosensor to video image signals. Following an integration period, the image signal charges formed on the photosensors are amplified and transferred as analog video signals to a common output line or bus through successively actuated multiplexing transistors.
For high-performance image sensor arrays, a preferred design includes an array of photosensors of a width comparable to the width of a page being scanned, to permit imaging generally without the use of reductive optics. In order to provide such a “full-width” array, however, relatively large silicon structures must be used to define the large number of photosensors. A preferred technique to create such a large array is to make the array out of several butted silicon chips. In one design, an array is intended to be made of twenty silicon chips, butted end-to-end, each chip having 248 active photosensors spaced at 400 photosensors per inch. Typically, the chips which are butted to form the array are formed in a silicon wafer, which is then “diced” into a number of chips, which are individually tested and then arranged into a bar shape.
In a sensor array of this design, each of the chips is a separate integrated circuit. Typically, each chip has its own individual video output, for the downloading of image signals ultimately from the photosensors on that particular chip. When an image is being scanned, video signals are output from each chip at a very high rate as the original hard-copy image moves past the linear array of photosensors on the chip. Thus, if the intended resolution of the chip in a bar is 400 spots per inch, a line of video data must be output from the chip every time the original image moves 1/400th of an inch. For this reason, in a bar with up to twenty chips, high-speed handling of the resulting video data becomes an important design consideration for downstream circuitry.
A key factor in designing circuitry downstream of such an image sensor array is how many parallel channels of digital data the circuitry is designed to accept. The outputs of many chips can be coordinated to output their video signals on to a single video line for all chips; conversely a large number of chips can each simultaneously output their video data in parallel. Of course, other designs may compromise between series and parallel outputs, such as combining the outputs of twenty chips into 2, 4, 5, 10 or 20 output lines. In general, the larger the number of chips grouped into a single output channel, the slower the maximum possible scan rate for the array. Conversely, the smaller the number of chips grouped into one output channel, the higher the maximum possible scan rate. Of course, whether the output is highly parallel or highly in series may introduce costs to the design, either in hardware or in performance. Therefore, it is desirable to provide an image sensor bar that can be electronically configured, so that a bar of a single design can be made to output as few or as many parallel channels as needed.